This was the research paper which introduced the abbreviation "VLIW" and contrasted it with the concept of RISC, which had been introduced a few years earlier.
At that time, the easiest way to understand the difference between RISC and VLIW CPUs and earlier CPUs was to compare them with the microprogrammed CPUs of the seventies, which used either "vertical microprogramming" or "horizontal microprogramming".
RISC CPUs could be viewed as modified vertically microprogrammed CPUs and VLIW CPUs could be viewed as modified horizontally microprogrammed CPUs.
In both cases the modification consisted in replacing the read-only microprogram memory with a read-write cache memory and eliminating the decoder that converted complex instructions into simple vertical microinstructions or horizontal microinstructions.
Thus what was previously the simpler instruction set used in microprograms became the programmer-visible ISA.
The term "vertical" had been applied to microinstructions that executed one simple operation per clock cycle, while "horizontal" was applied to microinstructions that executed in parallel multiple simple operations per clock cycle. Horizontal microinstructions differed from vector instructions a.k.a. SIMD instructions, because for each concurrent operation it is possible to specify in the encoding distinct source and destination registers from those used by the concurrent operations.
this gave me some old Itanic nostalgia just reading the foreword. There were some interesting discussions from 2024 regarding it and other people involved in VLIW designs
This was the research paper which introduced the abbreviation "VLIW" and contrasted it with the concept of RISC, which had been introduced a few years earlier.
At that time, the easiest way to understand the difference between RISC and VLIW CPUs and earlier CPUs was to compare them with the microprogrammed CPUs of the seventies, which used either "vertical microprogramming" or "horizontal microprogramming".
RISC CPUs could be viewed as modified vertically microprogrammed CPUs and VLIW CPUs could be viewed as modified horizontally microprogrammed CPUs.
In both cases the modification consisted in replacing the read-only microprogram memory with a read-write cache memory and eliminating the decoder that converted complex instructions into simple vertical microinstructions or horizontal microinstructions.
Thus what was previously the simpler instruction set used in microprograms became the programmer-visible ISA.
The term "vertical" had been applied to microinstructions that executed one simple operation per clock cycle, while "horizontal" was applied to microinstructions that executed in parallel multiple simple operations per clock cycle. Horizontal microinstructions differed from vector instructions a.k.a. SIMD instructions, because for each concurrent operation it is possible to specify in the encoding distinct source and destination registers from those used by the concurrent operations.
this gave me some old Itanic nostalgia just reading the foreword. There were some interesting discussions from 2024 regarding it and other people involved in VLIW designs
https://news.ycombinator.com/item?id=39097504