So they haven’t actually put any qubits on this, they just proven a novel way to fabricate _potential_ qubit architecture.
I’m still sceptical if quantum will take off in the foreseeable future if ever. Many people I talk to (laypeople like me) seem to think that QC is imminent and we need to prepare for it now.
We are still in the beginning stages of understanding whether scalable architectures are physically manufacturable at all.
> Imec has succeeded in fabricating a functioning network of qubits with gaps of barely 6 nanometers. Thanks to the nanoscale of this hardware component, millions of quantum bits can theoretically be integrated onto a single chip.
> This demonstration builds on imec’s previous results with silicon quantum dot spin qubits, which already demonstrated that CMOS-compatible processes can lead to low charge noise and stable qubit operation. By adding High NA EUV lithography to the production process, the focus shifts from individual demonstration devices in the lab to 300mm fab-compatible, reproducible quantum bits.
Based on their previous publication from 2025 that used 0.33 NA EUV, I'd expect another 3x5 qubit device, operating in a 10 mK environment.
So they haven’t actually put any qubits on this, they just proven a novel way to fabricate _potential_ qubit architecture.
I’m still sceptical if quantum will take off in the foreseeable future if ever. Many people I talk to (laypeople like me) seem to think that QC is imminent and we need to prepare for it now.
We are still in the beginning stages of understanding whether scalable architectures are physically manufacturable at all.
They did, just not disclosing how many:
> Imec has succeeded in fabricating a functioning network of qubits with gaps of barely 6 nanometers. Thanks to the nanoscale of this hardware component, millions of quantum bits can theoretically be integrated onto a single chip.
> This demonstration builds on imec’s previous results with silicon quantum dot spin qubits, which already demonstrated that CMOS-compatible processes can lead to low charge noise and stable qubit operation. By adding High NA EUV lithography to the production process, the focus shifts from individual demonstration devices in the lab to 300mm fab-compatible, reproducible quantum bits.
Based on their previous publication from 2025 that used 0.33 NA EUV, I'd expect another 3x5 qubit device, operating in a 10 mK environment.
If you want to test if scaling works, you gotta scale it first.
Lemme guess. No Shor?